2006/05/27 nand latch simulation with zero delay

2006/05/27 nand latch simulation with zero delay

module test_Nand_Latch_1;
reg preset,clear;
wire q,qbar;
Nand_Latch_1 M1(q,qbar,preset,clear);
initial
begin
$monitor($time,"preset=%b clear=%b q=%b qbar=%b",preset,clear,q,qbar);
end
initial

begin
#10preset=0;
#20 preset=1;
#30 clear=0;
#40clear=1;
#50 preset=0;
end initial
#60 $finish;
endmodule


module Nand_Latch_1 (q,qbar,preset,clear);
output q,qbar;
input preset,clear;
nand G1(q,preset,qbar); nand G2(qbar,clear,q);
endmodule

2006--5-19

2 bits 程式碼

2 bits 程式碼

module top;
reg A0,A1,B0,B1;
compare m1(A_it_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
initial begin A0=0; A1=0; B0=0; B1=0;
end always #100 A0=~A0;
always #160 A1=~A1;
always #200 B0=~B0;
always #440 B1=~B1;
endmodule
module compare(A_it_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_it_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or (A_it_B,w1,w2,w3);
nor (A_gt_B,A_it_B,A_eq_B);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and (w2,w6,w7,B0);
and (w3,w7,B0,B1);
not (w6,A1);
not (w7,A0);
xnor (w4,A1,B1);
xnor (w5,A0,B0);
endmodule